1. Field of Invention
Various embodiments of the present disclosure generally relate to semiconductor devices and methods of manufacturing the same and, more particularly, to semiconductor devices including bipolar transistors, CMOS transistors and DMOS transistors, and methods of manufacturing the same.
2. Description of Related Art
A semiconductor device including bipolar transistors, complementary metal-oxide-semiconductor (CMOS) transistors and double diffused metal-oxide-semiconductor (DMOS) transistors may be referred to as a BCDMOS device. The BCDMOS device may have some advantages of high frequency and high voltage operation characteristics due to the bipolar transistors, low power consumption, and high integration density due to the CMOS transistors, and excellent power controllability due to a low on-resistance between a drain and a source of each DMOS transistor. That is, the BCDMOS device may include high power circuits with large driving currents and logic circuits with low power consumption. However, fabrication of the BCDMOS device may need complex process technologies and a large number of photo masks. Thus, manufacturing costs of the BCDMOS device may be increased. Therefore, various process technologies for forming the BCDMOS device may still be required to reduce the manufacturing costs and to improve performance thereof.
The BCDMOS devices have been continuously developed to meet the requirements for both the high integration density of the CMOS transistors constituting the logic circuits and the low on-resistance of the DMOS transistors constituting high voltage circuits. A relatively narrow and deep isolation layer may be required to increase the integration density of the logic circuits. In contrast, a relatively gentle and shallow field oxide layer on which a field plate is located may be required to reduce the on-resistance of the DMOS transistors, for example, lateral double diffused metal-oxide-semiconductor (LDMOS) transistors. The logic circuits employed in the conventional power management integrated circuits (PMICs) may have a relatively simple configuration. Thus, process developments of the conventional PMICs have focused on the LDMOS transistors rather than the CMOS transistors. That is, the conventional BCDMOS devices have been developed to reduce the on-resistance of the LDMOS transistors. For example, shallow trenches with a relatively gentle sloped sidewall have been widely used to increase the on-resistance of the LDMOS transistors.
As functions of the PMICs become more complicated, areas that the logic circuits occupy have been gradually increased. Thus, when the aforementioned isolation technologies are applied to fabrication of the CMOS transistors used in realization of the logic circuits, the chip sizes of the BCDMOS devices including the logic circuits may increase. Accordingly, new process technologies, which are commonly applicable to both the CMOS transistors and the LDMOS transistors, may be required to improve both the integration density of the CMOS transistors and the on-resistance of the LDMOS transistors.